XILINX ZYNQ7000 development platform development board (model: AX7015) 2018 officially launched, in order to let you to this development platform can quickly understand, we write the user manual.

The ZYNQ7000 FPGA development platform adopts the core plate model, extension plates with convenient for the user to the secondary development and utilization of the core board.Core board using XILINX Zynq7000 XC7Z015 SOC chip solution, it USES the + FPGA SOC technology will dual-core architecture A9 and the FPGA programmable logic integrated on a chip.Another core board 2 slices containing a total of 1 gb DDR3 high-speed SDRAM chip, 1 piece of 8 gb eMMC memory chips and 1 piece of 256 MB of QSPI FLASH chips.

On bottom plate design we expanded the abundant peripheral interface for the user, such as a PCIex2 interface, two-way optical fiber interface, 2 gigabit Ethernet interface, 4 usb HOST interface, 1 HDMI input interface, 1 HDMI output interface, UART serial interface, 1 road 1 SD card interface, a 40 extension interface and so on.Meet the users various high-speed data exchange,Data is stored, video transmission process and to meet the requirements of industrial control, is a "professional" the ZYNQ development platform.For high-speed data transmission and exchange, in the early period of the data processing

Based on dual-core CortexA9 application processor, - v7 architecture is as high as 766 MHZ - 32 KB each CPU 1 level instruction and data cache, 512 KB level 2 cache 2 CPU sharing - the on-chip boot ROM and 256 KB on chip RAM - external storage interface, support 16/32 bit DDR2, DDR3 interfaces - two gigabit nic support: divergent - gathered the DMA, GMII, RGMII, SGMII interface - two usb OTG interface, each maximum 12 nodes - two CAN2.0 B bus interface - two SD CARDS, SDIO, MMC compatible controller - 2 SPI, 2 UARTs, two I2C interface - 4 set of 32 bit GPIO, 54 (32 + 22) as IO PS system, connected to the PL - 64 PS and PS to PL high bandwidth connections

The PL Logic part of the main parameters as follows: - a logical unit Logic Cells: 74 k;- a lookup table LUTs: 46200 - trigger (flip flops) : 92400-18 x25maccs multiplier: 160;- Block RAM: 3.3 Mb;High-speed GTP transceiver made - 4 road, support PCIE Gen2x4;

- 2 AD converter, can measure the voltage, temperature sensing and 17 external differential input channels, 1 MBPS

XC7Z015-2 clg485i chip speed was 2 grade, industrial-grade, encapsulation for BGA484, pin spacing of 0.8 mm, ZYNQ7000 series of specific models defined as shown in the diagram below the 2-2-2 chip.